Many approaches have been developed to test and verify interconnects and functionality of integrated circuits (ICs). Existing testing can utilize circuitry external to an IC for a various types of testing, circuitry internal to the IC, or a combination of internal and external circuitry and test equipment.
For example, ICs can be tested both before and after they are assembled into packages (e.g. dual-in-line packages or DIPs, leadless chip carriers or LCCs, pin grid arrays, quad flat packs, etc.). Before assembly into a package, ICs can be probed by special machines utilizing special probe cards and test vectors which consist of sets of input signals, output signals and bi-directional signals. These test vectors are used to provide information to the probe machine such that the IC can be electrically stimulated and verified. Each vector contains a set of input signals (stimulus) and a set of output signals which are verified by the probe machine after application of the input stimulus for each test vector. Once the preassembled ICs are verified to be functional, they are assembled into a packaged part and retested using similar types of apparatuses, which is now equipped with a package socket instead of a set of die pad probes. The same set of test vectors is utilized to verify post assembly operation.
As a further example, IEEE standard 1149.1 (also known as the Joint Test Action Group (JTAG) Standard) establishes a boundary scan implementation for IC interconnect testing. The JTAG standard is a scan-based architecture disposed on the IC under test as a part of the circuitry. Such an IC includes a scan input (receives serial data at an input pin) and a scan output (receives serial data from the ASIC at an output pin). Integrated circuits have increasingly incorporated the JTAG (Joint Test Action Group) test port to facilitate testing and debug of integrated circuit chips mounted on a board. The JTAG standard can be utilized in verification of both the ASICs and board level interconnect after the IC has been mounted onto a circuit board.
Under normal operating conditions, the boundary scan cells simply let the input/output signals pass through them, into and out of the I/O pins. When the device is placed into a ‘Test’ mode, however, these boundary scan cells become ‘active’ to enable the capture or control of the signals propagating into and out of the IC, effectively circumventing the device's normal input and output connections.